A number of types of languages are used when designing LSIs and ASICs. High-level languages such as “C” that have a high degree of abstraction are languages on a procedural level and are suited to showing how an entire process is executed in order on an instruction-by-instruction basis. Description on this level normally has no hardware dependency, is composed of application programs that can be received by a suitable computer, and is normally used to describe the specification of an LSI or an entire process executed by an LSI. Hardware description languages (HDL) such as Verilog-HDL or VHDL are also referred to as RTL and are used to describe, on a register transfer level, paths of special-purpose hardware for executing special-purpose instructions and/or a sequence for driving such data paths.
An algorithm is defined as a group of a limited number of rules that are precisely defined to solve a problem and are performed with a given order. In conventional parallel processing, among an entire process (application) described by an algorithm proceeds to be performed in an order, some parts (processes) that can be independently executed are performed in parallel to reduce the processing time. When an application is executed by a system including hardware resources that are suited to parallel processing in advance, the parts that can be processed in parallel are converted to parallel processes by a compiler in an attempt to improve the execution speed.
Also, when hardware is designed with the object of executing a dedicated application, a circuit is designed so as to process the parts in parallel, if the parts can be independently executed, with the aim of reducing the processing time. A technology disclosed by Japanese Laid-Open Patent Publication No. H10-116302 is a method of designing a circuit for a process where the execution time is uncertain using HDL with parallel processing and synchronized communication. In the synchronized communication, when two functions are executed in parallel, receiver process included in the two functions waits until the transmitter side can prepare, then the process proceeds after communication is completed. Accordingly, even though the functions are described in parallel, the functions are not carried out independently and therefore the execution time of the processing varies. On the other hand, processes that do not require synchronized communication are performed independently as parallel processes. These are technologies with an object of reducing the number of execution cycles by executing processes, out of the entire process provided in the source language, that are written so as to be executed in parallel on a source program, so as to be executed in parallel or with using synchronized communication in the hardware design.
In recent years, hardware for enabling parts of circuits constructing LSIs reconfigurable by software has been provided. International Publication WO03/007155 discloses a technology that includes the fundamental units for reconfiguring of operation unit level, not a gate level, that are equipped with arithmetic and/or logical functions of a certain scale, such as ALUs, and disposes a plurality of types of operation units in a matrix so that the time required by reconfiguration can be reduced. Since the operation units in such a system where a plurality of operation units are disposed in a matrix are respectively capable of executing processes in parallel, the system can be thought of as having hardware resources suited to a huge number of parallel processes. However, a design system suited to designing a system that is suited to this type of parallel processing has not been provided.
High-level languages such as “C” that are suited to software design have a premise of processing an algorithm with the rules included in the algorithm in a temporal order or in a time sequential. Accordingly, a configuration is used where instructions are sequentially executed as a program counter advances, with it being difficult to introduce parallel concepts that are not sequential. Even if the describing of instructions in parallel is permitted, this is limited to spatially expanding processes that can be independently executed in parallel within a range where the temporal order is not violated, and it is not Possible to aggressively use hardware resources suited to parallel processing. In addition, since instructions that do not depend on hardware are described in a high-level language, it is unclear at what timing instructions described in parallel will actually start and end on the hardware. Accordingly, even if the hardware space for processing is spatially expanded, the designer will not be able to define or even grasp what kind of parallel processing is actually carried out on the hardware.
Since HDL describes circuit arrangements that operate independently, it is fundamentally able to describe parallel processing. Also, since it is clear what the hardware is, it will be possible to investigate and adjust the timing at which processing is executed. For this reason, it is possible to write HDL descriptions that will realize an algorithm given in a high-level language. However, since HDL description is written with the premise of specific hardware, there is no general-purpose applicability, and it is not possible to realize the same algorithm on different hardware. In addition, if the hardware for which the HDL description has been written is not known, it will not be possible to understand the algorithm included in that HDL description.
At the level of microprograms obtained as a result of compiling high-level language for specific or particular hardware, there are technologies such as VLIW where instructions that can be executed completely independently are written in parallel and superscalar techniques where a plurality of instructions are simultaneously fetched and instructions that can be executed in parallel are found. These technologies improve the execution speed by executing processes, out of the processes that are arranged in temporal order, which can be performed spatially in parallel on a plurality of pipelines provided for executing such processes, and are no different to high-level languages in that a part of process where the temporal order is not violated is spatially expanded. That is, microprograms themselves are programming language and therefore sequential processing where instructions are executed in order as a program counter advances is also required for the VLIW and superscalar technologies. In addition, microprograms have a premise of special-purpose hardware and lack general-purpose applicability in the same way as HDL.
In this way, out of programming languages that are executed as a program counter advances, high-level languages have general-purpose applicability and facilitate software design, but the parts that can be spreading to parallel processing are limited to processes that can be executed independently of the program counter advancing, and it is difficult to effectively use operation units suited to a large number of parallel processes. Also, for high-level languages that do not depend on hardware, the timing of parallel processing is not known, and therefore a design that effectively executes an application by using a large number of operation units disposed in a matrix in parallel is not possible. Although it is possible to describe parallel processing in HDL, even if an algorithm is described in HDL, it is only possible to describe an algorithm with a premise of specific hardware, and therefore knowledge of the specific or particular hardware is required. It is not easy for a software technician to understand the functions, input and output timing, and the like of many types of operation units disposed in a matrix for designing an application in HDL.